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this is information on a product in full production. april 2013 doc id 17943 rev 5 1/129 1 stm8l151x8 stm8l152x8 stm8l151r6 stm8l152r6 8-bit ultralow power mcu, up to 64 kb flash + 2 kb data eeprom, rtc, lcd, timers, usarts, i2c, spis, adc, dac, comparators datasheet ? production data features operating conditions ? operating power supply: 1.65 to 3.6 v (without bor), 1.8 to 3.6 v (with bor) ? temp. range: -40 to 85, 105 or 125 c low power features ? 5 low power modes: wait, low power run (5.9 a), low power wait (3 a), active-halt with full rtc (1.4 a), halt (400 na) ? consumption: 200 a/mhz+330 a ? fast wake up from halt mode (4.7 s) ? ultra low leakage per i/0: 50 na advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq: 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources reset and supply management ? low power, ultrasafe bor reset with 5 programmable thresholds ? ultralow power por/pdr ? programmable voltage detector (pvd) clock management ? 32 khz and 1-16 mhz crystal oscillators ? internal 16 mhz factory-trimmed rc and 38 khz low consumption rc ? clock security system low power rtc ? bcd calendar with alarm interrupt, ? digital calibration with +/- 0.5ppm accuracy ? advanced anti-tamper detection dma ? 4 ch. for adc, dacs, spis, i 2 c, usarts, timers, 1 ch. for memory-to-memory lcd: 8x40 or 4x44 w/ step-up converter 12-bit adc up to 1 msps/28 channels ? temp. sensor and internal ref. voltage memories ? up to 64 kb of flash memory with up to 2 kb of data eeprom with ecc and rww ? flexible write/read protection modes ? up to 4 kb of ram 2x12-bit dac (dual mo de) with output buffer 2 ultralow power comparators ? 1 with fixed threshold and 1 rail to rail ? wakeup capability timers ? three 16-bit timers with 2 channels (ic, oc, pwm), quadrature encoder ? one 16-bit advanced control timer with 3 channels, supporting motor control ? one 8-bit timer with 7-bit prescaler ? 1 window and 1 independent watchdog ? beeper timer with 1, 2 or 4 khz frequencies communication interfaces ? two synchronous serial interface (spi) ?fast i 2 c 400 khz smbus and pmbus ? three usarts (iso 7816 interface + irda) up to 67 i/os, all mappab le on interrupt vectors up to 16 capacitive sensing channels supporting touchkey, proximity, linear touch and rotary touch sensors fast on-chip programming and non-intrusive debugging with swim, bootloader using usart 96-bit unique id table 1. device summary reference part number stm8l151x8 stm8l152x8 stm8l151c8, stm8l152c8, stm8l151r8, stm8l152r8, stm8l151m8, stm8l152m8 stm8l151r6 stm8l152r6 stm8l151r6, stm8l152r6 lqfp80 lqfp64 lqfp48 ufqfpn48 www.st.com
contents stm8l15xx8, stm8l15xr6 2/129 doc id 17943 rev 5 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 stm8l ultralow power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 ultralow power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.6 lcd (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.7 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.11 ultralow power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.12 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 21 3.13 touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.14.1 16-bit advanced control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14.2 16-bit general purpose timers (tim2, tim3, tim5) . . . . . . . . . . . . . . . . 22 3.14.3 8-bit basic timer (tim4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 stm8l15xx8, stm8l15xr6 contents doc id 17943 rev 5 3/129 3.15.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.16 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.2 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.18 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 9.3.2 embedded reset and power control block characteristics . . . . . . . . . . . 69 9.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.3.6 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.3.7 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 contents stm8l15xx8, stm8l15xr6 4/129 doc id 17943 rev 5 9.3.8 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.3.9 lcd controller (stm8l152xx only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 9.3.10 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 9.3.11 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.12 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3.13 12-bit dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9.3.14 12-bit adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.3.15 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 10 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 10.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 11 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 stm8l15xx8, stm8l15xr6 list of tables doc id 17943 rev 5 5/129 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. high density and medium+ density stm8l15xx low power device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 5. high density and medium+ density stm8l15x pin description . . . . . . . . . . . . . . . . . . . . . 28 table 6. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 8. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 9. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 10. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 11. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 12. option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 13. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 14. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 15. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 16. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 17. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 18. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 19. embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 20. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 21. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 22. total current consumption and timing in low power run mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 23. total current consumption in low power wait mode at vdd = 1.65 v to 3.6 v . . . . . . . . . 80 table 24. total current consumption and timing in active-halt mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 25. typical current consumption in active-halt mode, rtc clocked by lse external crystal . . 84 table 26. total current consumption and timing in halt mode at vdd = 1.65 to 3.6 v . . . . . . . . . . . 85 table 27. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 28. current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 29. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 30. lse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 31. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 32. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 33. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 34. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 35. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 36. flash program and da ta eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 37. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 38. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 39. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 40. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 41. output driving current (pa0 wi th high sink led driver capability). . . . . . . . . . . . . . . . . . . . 98 table 42. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 43. spi1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 44. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 45. lcd characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 list of tables stm8l15xx8, stm8l15xr6 6/129 doc id 17943 rev 5 table 46. reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 47. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 48. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 49. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 50. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 51. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 52. dac output on pb4-pb5-pb6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1 table 53. adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 54. adc1 accuracy with vdda = 3.3 v to 2.5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 55. adc1 accuracy with vdda = 2.4 v to 3.6 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 56. adc1 accuracy with vdda = vref+ = 1.8 v to 2.4 v. . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 57. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 58. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 59. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 60. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 table 61. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 62. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 63. 80-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 64. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 123 table 65. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 124 table 66. ufqfpn48 ? ultra thin fine pitch quad flat pack no-lead 7 7 mm, 0.5 mm pitch package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 67. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 68. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 stm8l15xx8, stm8l15xr6 list of figures doc id 17943 rev 5 7/129 list of figures figure 1. high density and medium+ density stm8l15xx device block diagram . . . . . . . . . . . . . . 13 figure 2. clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. stm8l151m8 80-pin package pinout (without lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4. stm8l152m8 80-pin package pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. stm8l151r8 and stm8l151r6 64-pin pinout (without lcd). . . . . . . . . . . . . . . . . . . . . . 26 figure 6. stm8l152r8 and stm8l152r6 64-pin pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. stm8l151c8 48-pin pinout (without lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 8. stm8l152c8 48-pin pinout (with lcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 10. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 11. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 12. power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 13. typical i dd(run) from ram vs. v dd (hsi clock source), f cpu =16 mhz . . . . . . . . . . . . . . 74 figure 14. typical i dd(run) from flash vs. v dd (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . 74 figure 15. typical i dd(wait) from ram vs. v dd (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . . 77 figure 16. typical i dd(wait) from flash (hsi clock source), f cpu = 16 mhz . . . . . . . . . . . . . . . . . . . . 77 figure 17. typical i dd(lpr) vs. v dd (lsi clock source), all peripherals off . . . . . . . . . . . . . . . . . . . . 79 figure 18. typical i dd(lpw) vs. v dd (lsi clock source), all peripherals off . . . . . . . . . . . . . . . . . . . 81 figure 19. typical idd(ah) vs. v dd (lsi clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 20. typical idd(halt) vs. v dd (internal reference voltage off) . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 21. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 22. lse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 figure 23. typical hsi frequency vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 24. typical lsi clock source frequency vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 25. typical vil and vih vs. vdd (standard i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 26. typical vil and vih vs. vdd (true open drain i/os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 27. typical pull-up resistance r pu vs. v dd with vin=vss. . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 28. typical pull-up current i pu vs. v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 29. typical vol @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 30. typical vol @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 31. typical vol @ vdd = 3.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 32. typical vol @ vdd = 1.8 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 33. typical vdd - voh @ vdd = 3.0 v (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 34. typical vdd - voh @ vdd = 1.8 v (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 35. typical nrst pull-up resistance r pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 36. typical nrst pull-up current i pu vs. v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 37. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 38. spi1 timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 39. spi1 timing diagram - slave mode and cpha=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 40. spi1 timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 figure 41. typical application with i2c bus and timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 42. adc1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 43. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 44. maximum dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 45. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . 117 figure 46. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . 117 figure 47. 80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 list of figures stm8l15xx8, stm8l15xr6 8/129 doc id 17943 rev 5 figure 48. lqfp64 ? 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 123 figure 49. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 50. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 51. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 52. ufqfpn48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 53. recommended footprint (dimensions in mm) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 stm8l15xx8, stm8l15xr6 introduction doc id 17943 rev 5 9/129 1 introduction this document describes the features, pinout, mechanical data and ordering information for: high density stm8l15xxx devices: stm8l151x8 and stm8l152x8 microcontrollers with a flash memory density of 64 kbytes. medium+ density stm8l15xxx devices : stm8l151r6 and stm8l152r6 microcontrollers with flash memory density of 32 kbytes. for further details on the stmicroelectroni cs ultralow power family please refer to section 2.3: ultralow power continuum on page 12 . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). 2 description the high density and medium+ density stm8l15xx ultralow power devices feature an enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. the family includes an integrated debug module with a hardware interface (swim) which allows non-intrusive in-application debugging and ultrafast flash programming. all high density and medium+ density stm8l15xx microcontrollers feature embedded data eeprom and low power low-voltage si ngle-supply program flash memory. the devices incorporate an extensive range of enhanced i/os and peripherals, a 12-bit adc, two dacs, two comparators, a real-time clock, four 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two spis, an i 2 c interface, and three usarts. a 8x40 or 4x44-segment lcd is available on the stm8l152x8 devices. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families including 32-bit families. this ma kes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. description stm8l15xx8, stm8l15xr6 10/129 doc id 17943 rev 5 2.1 stm8l ultralow power 8-bit family benefits high density and medium+ density stm8l15xx devices are part of the stm8l ultralow power family providing the following benefits: integrated system ? up to 64 kbytes of high-density embedded flash program memory ? up to 2 kbytes of data eeprom ? up to 4 kbytes of ram ? internal high-speed and low-power low speed rc. ? embedded reset ultralow power consumption ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for lo w power wait mode and low power run mode advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory-to-memory or peripheral-to-memory access. short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals. ? wide choice of development tools stm8l ultralow power microcontrollers can operate either from 1.8 to 3.6 v (down to 1.65 v at power-down) or from 1.65 to 3.6 v. they are available in the -40 to +85 c and -40 to +125 c temperature ranges. these features make the stm8l ultralow powe r microcontroller families suitable for a wide range of applications: medical and handheld equipment application control and user interface pc peripherals, gaming, gps and sport equipment alarm systems, wired and wireless sensors metering the devices are offered in four different packages from 48 to 80 pins. different sets of peripherals are included depending on the device. refer to section 3 for an overview of the complete range of peripherals proposed in this family. all stm8l ultralow power products are based on the same architecture with the same memory mapping and a coherent pinout. figure 1 shows the block diagram of the high density and medium+ density stm8l15xx families. stm8l15xx8, stm8l15xr6 description doc id 17943 rev 5 11/129 2.2 device overview table 2. high density and medium+ density stm8l15xx low power device features and peripheral counts features stm8l15xc8 stm8l1 5xr8 stm8l15xm8 stm8l15xr6 flash (kbytes) 64 64 64 32 data eeprom (kbytes) 2 1 ram (kbytes) 4 4 4 2 lcd 8x24 or 4x28 (1) 8x36 or 4x40 (1) 8x40 or 4x44 (1) 8x36 or 4x40 (1) timers basic 1 (8-bit) 1 (8-bit) 1 (8-bit) 1 (8-bit) general purpose 3 (16-bit) 3 (16-bit) 3 (16-bit) 3 (16-bit) advanced control 1 (16-bit) 1 (16-bit) 1 (16-bit) 1 (16-bit) communication interfaces spi 2 2 2 2 i2c 1 1 1 1 usart 3 3 3 3 gpios 41 (2) 54 (2) 68 (2) 54 (2) 12-bit synchronized adc (number of channels) 1 (25) 1 (28) 1 (28) 1 (28) 12-bit dac number of channels 2 2 2 2 2 2 2 2 comparators (comp1/comp2) 2 2 2 2 others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 to 3.6 v (down to 1.65 v at power-down) with bor 1.65 to 3.6 v without bor operating temperature ? 40 to +85 c / ? 40 to +105 c / ? 40 to +125 c packages ufqfpn48 lqfp48 lqfp64 lqfp80 lqfp64 1. stm8l152xx versions only. 2. the number of gpios given in this table includes the nrs t/pa1 pin but the application can use the nrst/pa1 pin as general purpose output only (pa1). description stm8l15xx8, stm8l15xr6 12/129 doc id 17943 rev 5 2.3 ultralow power continuum the ultralow power stm8l151xx and stm8l152xx are fully pin-to-pin, software and feature compatible. besides the full compatibility within the fam ily, the devices are part of stmicroelectronics microcontrollers ultralow power strategy which also includes stm8l101xx and stm32 l15xxx. the stm8l and stm32l families allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultralow leakage process. note: 1 the stm8l151xx and stm8l152xx are pin-to-pin compatible with stm8l101xx devices. 2 the stm32l family is pin-to-pin compatible with the general purpose stm32f family. please refer to stm32l15xx documentation for more information on these devices. performance all families incorporate highly energy-efficien t cores with both harvar d architecture and pipelined execution: advanced stm8 core fo r stm8l families and arm cortex?-m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultralow power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l151xx/152xx and stm32l15xx share identical peripherals which ensure a very easy migration from one family to another: analog peripherals: adc1, dac1/dac2, and comparators comp1/comp2 digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and optimize performance, the stm8l15xx and st m32l15xx devices use a common architecture: same power supply range from 1.65 to 3.6 v. for stm8l101xx and medium density stm8l15xx, the power supply must be above 1.8 v at power-on, and go below 1.65 v at power-down. architecture optimized to reach ultralow consumption both in low power modes and run mode fast startup strategy from low power modes flexible system clock ultrasafe reset: same reset strategy for both stm8l15xx and stm32l15xx including power-on reset, power-down reset, brownout reset and programmable voltage detector. features st utralow power continuum also lies in feature compatibility: more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm memory density ranging from 4 to 128 kbytes stm8l15xx8, stm8l15xr6 functional overview doc id 17943 rev 5 13/129 3 functional overview figure 1. high density and medium+ density stm8l15xx device block diagram 1. legend : af: alternate function adc: analog-to-digital converter bor: brownout reset dma: direct memory access dac: digital-to-analog converter i2c: inter-integrated circuit multimaster interface iwdg: independent watchdog a i b # l o c k c o n t r o l l e r a n d # 3 3 # l o c k s ! d d r e s s c o n t r o l a n d d a t a b u s e s + b y t e + b y t e 2 ! - t o c o r e a n d p e r i p h e r a l s ) 7 $ ' k ( z c l o c k 0 o r t ! 0 o r t " 0 o r t # 0 o w e r 6 / , 4 2 % ' , # $ d r i v e r 7 7 $ ' u p t o + b y t e 0 o r t $ 0 o r t % " e e p e r 2 4 # m e m o r y 0 r o g r a m $ a t a % % 0 2 / - 6 $ $ 6 $ $ 6 $ $ 6 6 3 3 3 7 ) - 3 # , 3 $ ! 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + ! $ # ? ) . x # / - 0 ? ) . 0 # / - 0 # / - 0 # / - 0 ? ) . 0 6 $ $ ! 6 3 3 ! 3 - " 6 $ $ ! 6 3 3 ! 4 e m p s e n s o r b i t ! $ # 6 2 % & |